The invention is in the field of metal-oxide-semiconductor (MOS) field-effect devices, and relates specifically to lateral double-diffused MOS (DMOS) field-effect transistors.
Such transistors are well-known in the art and a typical high-voltage DMOS transistor is shown on page 1325 of the "IEEE Transactions on Electron Devices", Vol. ED-25, No. 11, November 1978, in a paper entitled "Tradeoff Between Threshold Voltage and Breakdown in High-Voltage Double-Diffused MOS Transistors", by Pocha et al. This device includes a semiconductor substrate of a first conductivity type (p-type), an epitaxial surface layer of a second conductivity type (n-type) on the substrate, a surface-adjoining channel region of the first conductivity type in the epitaxial layer, a surface-adjoining source region of the second conductivity type in the channel region, and a surface-adjoining drain region of the second conductivity type in the epitaxial layer and spaced apart from the channel region. An insulating layer is provided on the epitaxial surface layer and covers at least that portion of the channel region located between the source and drain. A gate electrode is provided on the insulating layer, over a portion of the channel region between the source and drain and is electrically isolated from the epitaxial surface layer, while source and drain electrodes are connected respectively to the source and drain regions of the transistor. Such prior art high-voltage DMOS transistors typically have a relatively thick epitaxial layer, in the order of about 25-30 micrometers for a breakdown voltage of about 250 V, as indicated in the Pocha et al paper.
Generalized techniques for improving the high-voltage breakdown characteristics of p-n junctions are disclosed in U.S. Patent Application Ser. No. 913,026, filed June 6 1978, by V. Temple. Subsequently, it was found that the breakdown characteristics of high-voltage semiconductor devices could be improved using the REduced SURface Field or RESURF) technique, as described in "High Voltage Thin Layer Devices (RESURF Devices)", "International Electronic Devices Meeting Technical Digest", December, 1979, pages 238-240, by Appels et al, and U.S Pat. application Ser. No. 004,004, filed Jan. 16, 1979, by Appels et al, incorporated herein by reference. Essentially, the improved breakdown characteristics of RESURF devices are achieved by employing thinner but more highly doped epitaxial layers to reduce surface fields.
The RESURF technique was applied to lateral double-diffused MOS transistors, as reported in "Lateral DMOS Power Transistor Design", "IEEE Electron Device Letters", Vol. EDL-1, pages 51-53, April, 1978, by Colak et al, and the result was a substantial improvement in device characteristics. It should be understood that in high-voltage DMOS devices, there is always a trade-off between breakdown voltage and on-resistance, with the goal being to increase the breakdown voltage level while maintaining a relatively low on-resistance. Using the prior art RESURF technique, and for reference assuming a constant breakdown voltage, an improvement (e.g. decrease) in on-resistance by a factor of about 3 may be obtained in a device occupying the same area as a conventional (thick epitaxial layer) DMOS device. Nevertheless, a further improvement in the breakdown voltage and/or on-resistance characteristics of such devices is extremely desirable, in particular for high-voltage power devices where both breakdown voltage and on-resistance are important parameters. Alternatively, it would be desirable to provide DMOS devices with the same characteristics as prior art devices but which occupy a smaller area and are thus less expensive to produce.